1. Field of the Invention
The present invention relates to techniques for handling interrupts in a system having multiple data processing units, also referred to herein as a multi-processor system. It will be appreciated that the multiple data processing units, also referred to herein as processors, may take a variety of forms, for example CPUs, Direct Memory Access (DMA) controllers, etc, and indeed may comprise a combination of different processing devices.
2. Description of the Prior Art
When devices within a data processing system require a processor within the data processing system, typically the CPU, to perform a service routine, they will typically issue an interrupt request to that processor. When an interrupt request is received by the processor whilst it is executing a main process, the processor will typically temporarily interrupt the main process under execution, and instead execute the Interrupt Service Routine (ISR) specified by the interrupt request. The devices may be on the same chip as the processor, or may be off-chip. In a typical data processing system there will often be multiple devices which can issue such interrupt requests, and since the processor cannot simultaneously execute the ISRs defined by the plurality of interrupt requests, it is known to provide an interrupt controller for receiving the various interrupt requests, and prioritising between them. Hence, interrupt requests from certain devices (for example a network interface) can be given higher priority than interrupt requests from other devices (for example a keyboard).
In a vectored interrupt controller (VIC) the controller will store a list of vector addresses for ISRs that are associated with each interrupt source, i.e. each device that can issue an interrupt request. Hence, when an interrupt request is received, the VIC can pass the exact location of the associated ISR code to the processor to enable the processor to begin execution of that ISR.
As data processing systems become more complex, it is known to provide a plurality of processors within the data processing system for sharing the data processing load. Hence, in a typical multi-processor system, the operating system and the applications will be multi-threaded. In such systems, it is clear that the interrupt request servicing could also be distributed amongst the multiple processors. However, one problem that occurs is how to design an interrupt controller that can make effective use of the multiple processors within the system when processing interrupt requests.
U.S. Pat. No. 5,918,057 describes an interrupt processing technique suitable for use in an interrupt controller of a multi-processor system. For each interrupt source that can generate an interrupt request, the interrupt controller has a destination register identifying the particular processor(s) to which the corresponding interrupt request may be directed, and further includes a priority register containing information identifying the priority of the corresponding interrupt request relative to the other interrupt requests. The interrupt controller applies the received interrupt requests to a priority compare tree which serves to prioritise the received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. This process is performed with reference to the appropriate destination register. Similar determinations are then made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt.
Accordingly, it can be seen that the destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously.
Whilst such an approach can enable an increase in the throughput of interrupt requests by allowing simultaneous issue of interrupt requests, it cannot ensure that the highest priority interrupt request will necessarily be routed to the processor that will most quickly be able to service that interrupt request. For example, the highest priority interrupt request may be routed via the destination selection circuit to CPU0, whilst the next highest priority request might be routed via the destination selection circuit to CPU1. However, dependent on the processing being performed by both CPU0 and CPU1 at the time, CPU1 may be able to start servicing an interrupt request more quickly than CPU0. In this instance, it can be seen that, whilst the overall throughput of interrupt requests through the system is relatively high, the highest priority interrupt request has not been handled in the most expedient manner, since it has been routed to CPU0 rather than to CPU1.
It is an object of the present invention to provide a technique for processing interrupt requests in a multi-processor system which enables a highest priority interrupt request to be routed to the data processing unit which is able to service that interrupt request most quickly.